1. Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices and more specifically to a process sequence allowing fabrication of both high performance complimentary metal oxide semiconductor field effect transistor (CMOSFET) devices, and embedded dynamic random access memory E-DRAM devices, to be realized on the same semiconductor chip.
2. Description of Prior Art
In an effort to improve performance of specific CMOS devices used in the periphery of memory cells, fabrication of these devices have been accomplished in thin silicon layers residing on insulator. The use of a thin silicon layer on insulator, referred to as silicon on insulator (SOI), allows reductions of performance degrading capacitance to be realized thus reducing device delay time for the CMOS peripheral devices. Other type CMOS devices used for memory cells benefit via formation directly on a semiconductor substrate, or on a non-SOI region. Thus semiconductor chips are now being fabricated wherein CMOS logic type devices are formed on SOI regions on a semiconductor substrate, while CMOS memory type devices used for either E-DRAM, embedded static random access memory (E-SRAM), or embedded flash memory cells are formed on non-SOI regions of the same semiconductor substrate. The formation of SOI regions however can result in the peripheral devices being located on higher topographical surfaces of the semiconductor substrate, while the embedded memory devices are formed in recess regions of the same semiconductor substrate. This anomaly, the difference in height between the peripheral CMOS devices, and the embedded CMOS devices, can result in high aspect ratios for the definition procedure used to form openings in composite insulator layers used with both type devices.
This invention will describe a process sequence for fabrication of peripheral devices located on SOI regions, and for embedded devices located on recessed regions of a semiconductor substrate, featuring a reduction of the contact hole aspect ratio of the peripheral CMOS device, as well as a reduction of the aspect ratio of a capacitor plug opening in a recessed, embedded CMOS device. Prior art such as: Wu, in U.S. Pat. No. 6,121,662; Scott et al, in U.S. Pat. No. 4,754,314; Chen et al, in U.S. Pat. No. 6,214,653 B1; Leobanduag et al, in U.S. Pat. No. 6,214,694 B1; Hakey et al, in U.S. Pat. No. 6,232,170 B1; and Yamazaki et al, in U.S. Pat. No. 5,604,137, all describe methods of forming devices on both SOI and non-SOI regions. However none of these prior arts describe the key features supplied in this present invention allowing the aspect ratio of specific hole openings for devices formed on both SOI and directly on recessed portions of a semiconductor substrate, to be reduced.
It is an object of this invention to fabricate high performance CMOS devices on a SOI region of a semiconductor substrate, used for peripheral circuitry, while fabricating additional CMOS devices on recessed regions of a semiconductor substrate, used for embedded memory cell applications.
It is another object of this invention to reduce the contact hole aspect ratio for the high performance CMOS devices, and for the storage node plug opening of the CMOS devices in the embedded memory cells, via chemical mechanical polishing procedures, and the use of a silicon oxide removal procedure performed in the embedded memory region.
In accordance with the present invention a process for fabricating high performance CMOS devices on SOI regions in peripheral regions of a semiconductor substrate, and for fabricating CMOS devices for embedded memory cells on recessed portions of the same semiconductor substrate, featuring a reduction in the aspect ratio for contact hole openings and storage plug openings, is described. After formation of field oxide (FOX) regions on portions of a semiconductor substrate to be used for embedded memory cells, a silicon on insulator (SOI) layer is formed on portions of the semiconductor substrate not occupied by the FOX regions, to be used to accommodate the high performance peripheral CMOS devices. After removal of the FOX regions the CMOS devices for embedded memory cell applications is formed on the recessed portion of semiconductor, while higher performing CMOS devices are formed on the SOI region. After deposition of a first insulator layer, and a first planarization procedure, a top portion of the planarized first insulator layer is removed in the embedded memory region. A storage node plug opening and storage node plug structure are formed in the remaining bottom portion of the first insulator layer, with the aspect ratio of the storage node plug opening reduced via previous removal of the top portion of first insulator layer. A second insulator layer is deposited and planarized, resulting in a first composite insulator layer comprised of thin, planarized second insulator layer on first insulator layer, overlying the CMOS devices in the SOI region, and resulting in a second composite insulator layer comprised of a thicker second insulator layer component on a bottom portion of first insulator layer, in the embedded memory region. A capacitor structure is formed in an opening in the thicker second insulator layer of the second composite insulator layer, overlying and contacting the storage node plug structure. A contact hole opening is then formed in the first composite insulator layer exposing a portion of the CMOS source/drain region, in the SOI region, with the aspect ratio of the contact hole opening reduced as a result of the second planarization procedure.